The present invention relates to a semiconductor memory device; more particularly, to a semiconductor memory device capable of reducing a test time at a wafer level by excluding a method of receiving an internal reset signal through a specific external pin in a test mode.
FIG. 1 is a timing chart illustrating an entry of an initialization sequence reset at a power-on-state prescribed in Intel's DDR3 specification. Referring to FIG. 1, in order to enter a reset mode, a reset signal RESET should be maintained at a low level for at least 200 μs. Also, a clock enable signal CKE is inactivated at a low level within 10 ns before the reset signal is inactivated and this condition is maintained for 500 μs to initialize a DRAM. The clock enable sign CKE is in a stable state within 10 ns before a clock signal CLK and an external command signal CMD are applied to the memory device. At this time, the external command signal CMD is a NOP command or a chip deselect command.
FIG. 2 is a timing chart showing an entry of a reset mode in a power stabilization condition prescribed in Intel's DDR3 specification. Referring to FIG. 2, a reset signal RESET is activated in a high level for at last 100 ns while the power is stabilized. Also, a clock enable signal CKE goes to a low level within 10 ns before the reset signal is inactivated and this condition is maintained for 500 μs to initialize a DRAM. The clock enable signal CKE is in a stable state within 10 ns before a clock signal CLK and an external command signal CMD are applied to the memory device. At this time, the external command signal CMD is a NOP (no-operation) command or a chip deselect command.
On the other hand, a method for converting a reset command RSTB applied from an external circuit to an internal reset signal RESETB_OUT in order to provide the entry of the reset mode which is mentioned above, will be described below.
FIG. 3 is a block diagram illustrating a reset signal supplying unit in a conventional semiconductor memory device. Referring to FIG. 3, a reset signal generating unit includes a buffer 10 for receiving a reset command RSTB and a reset signal driving unit 20 for driving an internal reset signal RESETB_OUT using an output signal from the buffer 10. A block 30 including a clock buffer, an ODT (on-die termination) buffer and termination resistances enters the reset mode in response to the internal reset signal RESETB_OUT. Meanwhile, as to the device test at the wafer level, tests for a plurality of devices are simultaneously performed through single equipment for mass production. That is, the number of tested devices is determined based on the number of input pins of each device to be tested because the number of the input pins in the equipment is restricted. The more the number of devices to be tested one time are, the less the whole test time is.
However, as shown in FIG. 3, the reset command is applied only from the external pins and, as shown in FIGS. 1 and 2, the entry of the reset mode is not executed without the reset command from the external pins. Accordingly, a method for reducing the number of external input pins is required to reduce the test time at the wafer level.